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ISL9N306AD3 / ISL9N306AD3ST
June 2003
ISL9N306AD3 / ISL9N306AD3ST
N-Channel Logic Level PWM Optimized UltraFET(R) Trench Power MOSFETs 30V, 50A, 6m
General Description
This device employs a new advanced trench MOSFET technology and features low gate charge while maintaining low on-resistance. Optimized for switching applications, this device improves the overall efficiency of DC/DC converters and allows operation to higher switching frequencies.
Features
* Fast switching * rDS(ON) = 0.0052 (Typ), V GS = 10V * rDS(ON) = 0.0085 (Typ), V GS = 4.5V * Qg (Typ) = 30nC, VGS = 5V * Qgd (Typ) = 11nC * CISS (Typ) = 3400pF
SOURCE DRAIN DRAIN (FLANGE) GATE G S
Applications
* DC/DC converters
DRAIN (FLANGE)
D
GATE SOURCE
TO-252
TO-251
MOSFET Maximum Ratings TA = 25C unless otherwise noted
Symbol VDSS VGS Parameter Drain to Source Voltage Gate to Source Voltage Drain Current Continuous (TC = 25oC, VGS = 10V) ID Continuous (TC = 100oC, VGS = 4.5V) Continuous (TC = 25oC, VGS = V, RJC = 52oC/W) Pulsed PD TJ, TSTG Power dissipation Derate above 25oC Operating and Storage Temperature 50 50 16 Figure 4 125 0.83 -55 to 175 A A A A W W/oC
o
Ratings 30 20
Units V V
C
Thermal Characteristics
RJC RJA RJA Thermal Resistance Junction to Case TO-251, TO-252 Thermal Resistance Junction to Ambient TO-251, TO-252 Thermal Resistance Junction to Ambient TO-252, 1in2 copper pad area 1.2 100 52
o o o
C/W C/W C/W
Package Marking and Ordering Information
Device Marking N306AD N306AD Device ISL9N306AD3ST ISL9N306AD3 Package TO-252AA TO-251AA Reel Size 330mm Tube Tape Width 16mm N/A Quantity 2500 units 75 units
(c)2003 Fairchild Semiconductor Corporation
ISL9N306AD3 / ISL9N306AD3ST Rev. B2
ISL9N306AD3 / ISL9N306AD3ST
Electrical Characteristics TA = 25C unless otherwise noted
Symbol Parameter Test Conditions Min Typ Max Units
Off Characteristics
BVDSS IDSS IGSS Drain to Source Breakdown Voltage Zero Gate Voltage Drain Current Gate to Source Leakage Current ID = 250A, VGS = 0V VDS = 25V VGS = 0V VGS = 20V TC = 150o 30 1 250 100 V A nA
On Characteristics
VGS(TH) rDS(ON) Gate to Source Threshold Voltage Drain to Source On Resistance VGS = VDS, ID = 250A ID = 50A, VGS = 10V ID = 50A, VGS = 4.5V 1 3 V 0.0052 0.0060 0.0085 0.0095
Dynamic Characteristics
CISS COSS CRSS Qg(TOT) Qg(5) Qg(TH) Qgs Qgd Input Capacitance Output Capacitance Reverse Transfer Capacitance Total Gate Charge at 10V Total Gate Charge at 5V Threshold Gate Charge Gate to Source Gate Charge Gate to Drain "Miller" Charge VDS = 15V, VGS = 0V, f = 1MHz VGS = 0V to 10V VGS = 0V to 5V V = 15V DD VGS = 0V to 1V ID = 50A Ig = 1.0mA 3400 650 300 60 30 3.0 10 11 90 45 4.5 pF pF pF nC nC nC nC nC
Switching Characteristics (VGS = 4.5V)
tON td(ON) tr td(OFF) tf tOFF Turn-On Time Turn-On Delay Time Rise Time Turn-Off Delay Time Fall Time Turn-Off Time VDD = 15V, ID = 16A VGS = 4.5V, RGS = 4.3 16 70 34 30 131 97 ns ns ns ns ns ns
Switching Characteristics (VGS = 10V)
tON td(ON) tr td(OFF) tf tOFF Turn-On Time Turn-On Delay Time Rise Time Turn-Off Delay Time Fall Time Turn-Off Time VDD = 15V, ID = 16A VGS = 10V, R GS = 4.3 10 43 62 29 80 137 ns ns ns ns ns ns
Unclamped Inductive Switching
tAV Avalanche Time ID = 30A, L = 200H 428 s
Drain-Source Diode Characteristics
VSD trr QRR Source to Drain Diode Voltage Reverse Recovery Time Reverse Recovered Charge ISD = 50A ISD = 25A ISD = 50A, dISD /dt = 100A/s ISD = 50A, dISD /dt = 100A/s 1.25 1.0 35 30 V V ns nC
(c)2003 Fairchild Semiconductor Corporation
ISL9N306AD3 / ISL9N306AD3ST Rev. B2
ISL9N306AD3 / ISL9N306AD3ST
Typical Characteristic
1.2 60
POWER DISSIPATION MULTIPLIER
1.0 ID, DRAIN CURRENT (A)
50 VGS = 10V 40 VGS = 4.5V 30
0.8
0.6
0.4
20
0.2
10
0 0 25 50 75 100 125 150 175 TC , CASE TEMPERATURE (oC)
0 25 50 75 100 125 150 175 TC, CASE TEMPERATURE (oC)
Figure 1. Normalized Power Dissipation vs Ambient Temperature
2 1 DUTY CYCLE - DESCENDING ORDER 0.5 0.2 0.1 0.05 0.02 0.01
Figure 2. Maximum Continuous Drain Current vs Case Temperature
ZJC, NORMALIZED THERMAL IMPEDANCE
PDM 0.1 t1 t2 SINGLE PULSE NOTES: DUTY FACTOR: D = t1/t2 PEAK TJ = PDM x ZJC x RJC + TC 10-2 t, RECTANGULAR PULSE DURATION (s) 10-1 100 101
0.01 10-5
10-4
10-3
Figure 3. Normalized Maximum transient Thermal Impedance
2000
TC = 25oC FOR TEMPERATURES ABOVE 25oC DERATE PEAK CURRENT AS FOLLOWS: I = I25 VGS = 10V 175 - TC 150
IDM , PEAK CURRENT (A)
1000
VGS = 5V 100
40
TRANSCONDUCTANCE MAY LIMIT CURRENT IN THIS REGION 10-4 10-3 10-2 t, PULSE WIDTH (s) 10-1 100 101
10 -5
Figure 4. Peak Current Capability
(c)2003 Fairchild Semiconductor Corporation
ISL9N306AD3 / ISL9N306AD3ST Rev. B2
ISL9N306AD3 / ISL9N306AD3ST
Typical Characteristic (Continued)
100 PULSE DURATION = 80s DUTY CYCLE = 0.5% MAX VDD = 15V ID , DRAIN CURRENT (A) ID, DRAIN CURRENT (A) 75 75 100
VGS = 10V
VGS = 4.5V
VGS = 3.5V
50 TJ = 175oC 25 TJ = 25oC 0 1 2 3 4 5 TJ = -55oC
50 VGS = 3V 25
TC = 25 oC PULSE DURATION = 80s DUTY CYCLE = 0.5% MAX
0 0 0.5 1.0 1.5 2.0
VGS, GATE TO SOURCE VOLTAGE (V)
VDS , DRAIN TO SOURCE VOLTAGE (V)
Figure 5. Transfer Characteristics
25 NORMALIZED DRAIN TO SOURCE ON RESISTANCE PULSE DURATION = 80s DUTY CYCLE = 0.5% MAX TC = 25oC
Figure 6. Saturation Characteristics
2.0 PULSE DURATION = 80s DUTY CYCLE = 0.5% MAX
rDS(ON), DRAIN TO SOURCE ON RESISTANCE (m)
ID = 25A 20
1.5
15
10
ID =5A
ID = 50A
1.0
VGS = 10V, ID = 50A 5 2 4 6 8 10 0.5 -80 -40 0 40 80 120 160 200
VGS, GATE TO SOURCE VOLTAGE (V)
TJ, JUNCTION TEMPERATURE (oC)
Figure 7. Drain to Source On Resistance vs Gate Voltage and Drain Current
1.4 VGS = VDS, ID = 250A
Figure 8. Normalized Drain to Source On Resistance vs Junction Temperature
1.2 ID = 250A NORMALIZED DRAIN TO SOURCE BREAKDOWN VOLTAGE
NORMALIZED GATE THRESHOLD VOLTAGE
1.0
1.1
0.6
1.0
0.2 -80 -40 0 40 80 120 160 200
0.9 -80 -40 0 40 80 120 160 200
TJ, JUNCTION TEMPERATURE (oC)
TJ , JUNCTION TEMPERATURE (oC)
Figure 9. Normalized Gate Threshold Voltage vs Junction Temperature
Figure 10. Normalized Drain to Source Breakdown Voltage vs Junction Temperature
(c)2003 Fairchild Semiconductor Corporation
ISL9N306AD3 / ISL9N306AD3ST Rev. B2
ISL9N306AD3 / ISL9N306AD3ST
Typical Characteristic (Continued)
5000 CISS = CGS + C GD VGS , GATE TO SOURCE VOLTAGE (V) 8 C, CAPACITANCE (pF) COSS CDS + C GD 1000 CRSS = CGD 10 VDD = 15V
6
4 WAVEFORMS IN DESCENDING ORDER: ID = 50A ID = 25A ID = 5A 0 10 20 30 40 50 60
2
VGS = 0V, f = 1MHz 100 0.1 1 10 VDS , DRAIN TO SOURCE VOLTAGE (V) 30
0
Qg, GATE CHARGE (nC)
Figure 11. Capacitance vs Drain to Source Voltage
300 VGS = 4.5V, VDD = 15V, ID = 16A 250 SWITCHING TIME (ns)
Figure 12. Gate Charge Waveforms for Constant Gate Currents
500 VGS = 10V, VDD = 15V, I D = 16A 400 SWITCHING TIME (ns)
200 tr 150 tf
300 td(OFF) 200 tf 100 tr td(ON) 0 10 20 30 40 50
100 td(OFF) 50 td(ON) 0 0 10 20 30 40 50
0
RGS, GATE TO SOURCE RESISTANCE ()
RGS, GATE TO SOURCE RESISTANCE ()
Figure 13. Switching Time vs Gate Resistance
Figure 14. Switching Time vs Gate Resistance
Test Circuits and Waveforms
VDS tP L IAS VARY tP TO OBTAIN REQUIRED PEAK IAS VGS DUT tP 0V RG -
BVDSS
VDS VDD
+
VDD
IAS 0.01
0 tAV
Figure 15. Unclamped Energy Test Circuit
(c)2003 Fairchild Semiconductor Corporation
Figure 16. Unclamped Energy Waveforms
ISL9N306AD3 / ISL9N306AD3ST Rev. B2
ISL9N306AD3 / ISL9N306AD3ST
Test Circuits and Waveforms (Continued)
VDS RL
VDD VDS
Qg(TOT)
VGS = 10V VGS Qg(5) VDD DUT Ig(REF) 0 VGS VGS = 1V Qg(TH) Qgs Ig(REF) 0 Qgd VGS = 5V
+
Figure 17. Gate Charge Test Circuit
Figure 18. Gate Charge Waveforms
VDS
tON td(ON) RL VDS 90% tr
tOFF td(OFF) tf 90%
VGS
+
VDD DUT 0
10%
10%
90% VGS 50% PULSE WIDTH 50%
RGS
VGS
0
10%
Figure 19. Switching Time Test Circuit
Figure 20. Switching Time Waveforms
(c)2003 Fairchild Semiconductor Corporation
ISL9N306AD3 / ISL9N306AD3ST Rev. B2
ISL9N306AD3 / ISL9N306AD3ST
Thermal Resistance vs. Mounting Pad Area
The maximum rated junction temperature, TJM , and the thermal resistance of the heat dissipating path determines the maximum allowable device power dissipation, PDM , in an application. Therefore the application's ambient temperature, TA (oC), and thermal resistance RJA (oC/W) must be reviewed to ensure that TJM is never exceeded. Equation 1 mathematically represents the relationship and serves as the basis for establishing the rating of the part.
(T -T ) JM A P D M = ----------------------------Z J A
125 RJA = 33.32 + 23.84/(0.268+Area)
100
RJA (oC/W)
75
(EQ. 1)
50
In using surface mount devices such as the TO-252 package, the environment in which it is applied will have a significant influence on the part's current and maximum power dissipation ratings. Precise determination of P DM is complex and influenced by many factors: 1. Mounting pad area onto which the device is attached and whether there is copper on one side or both sides of the board. 2. The number of copper layers and the thickness of the board. 3. The use of external heat sinks. 4. The use of thermal vias. 5. Air flow and board orientation. 6. For non steady state applications, the pulse width, the duty cycle and the transient thermal response of the part, the board and the environment they are in. Fairchild provides thermal information to assist the designer's preliminary application evaluation. Figure 21 defines the RJA for the device as a function of the top copper (component side) area. This is for a horizontally positioned FR-4 board with 1oz copper after 1000 seconds of steady state power with no air flow. This graph provides the necessary information for calculation of the steady state junction temperature or power dissipation. Pulse applications can be evaluated using the Fairchild device Spice thermal model or manually utilizing the normalized maximum transient thermal impedance curve. Displayed on the curve are RJA values listed in the Electrical Specifications table. The points were chosen to depict the compromise between the copper board area, the thermal resistance and ultimately the power dissipation, PDM . Thermal resistances corresponding to other copper areas can be obtained from Figure 21 or by calculation using Equation 2. R JA is defined as the natural log of the area times a coefficient added to a constant. The area, in square inches is the top copper area including the gate and source pads.
25 0.01 0.1 1 10
AREA, TOP COPPER AREA (in2)
Figure 21. Thermal Resistance vs Mounting Pad Area
R JA = 33.32 + ------------------------------------
23.84 ( 0.268 + Area )
(EQ. 2)
(c)2003 Fairchild Semiconductor Corporation
ISL9N306AD3 / ISL9N306AD3ST Rev. B2
ISL9N306AD3 / ISL9N306AD3ST
PSPICE Electrical Model
.SUBCKT ISL9N306A 2 1 3 ; CA 12 8 2.0e-9 CB 15 14 2.3e-9 CIN 6 8 3e-9 DBODY 7 5 DBODYMOD DBREAK 5 11 DBREAKMOD DPLCAP 10 5 DPLCAPMOD EBREAK 11 7 17 18 35.8 EDS 14 8 5 8 1 EGS 13 8 6 8 1 ESG 6 10 6 8 1 EVTHRES 6 21 19 8 1 EVTEMP 20 6 18 22 1 IT 8 17 1 LDRAIN 2 5 1.0e-9 LGATE 1 9 4.58e-9 LSOURCE 3 7 1.47e-9 MMED 16 6 8 8 MMEDMOD MSTRO 16 6 8 8 MSTROMOD MWEAK 16 21 8 8 MWEAKMOD RBREAK 17 18 RBREAKMOD 1 RDRAIN 50 16 RDRAINMOD 1e-3 RGATE 9 20 2.69 RLDRAIN 2 5 10 RLGATE 1 9 45.8 RLSOURCE 3 7 14.7 RSLC1 5 51 RSLCMOD 1e-6 RSLC2 5 50 1e3 RSOURCE 8 7 RSOURCEMOD 3.5e-3 RVTHRES 22 8 RVTHRESMOD 1 RVTEMP 18 19 RVTEMPMOD 1 S1A S1B S2A S2B 6 12 13 8 S1AMOD 13 12 13 8 S1BMOD 6 15 14 13 S2AMOD 13 15 14 13 S2BMOD
S1A 12 13 8 13 + EGS 6 8 EDS S2A 14 13 S2B CB + 5 8 8 22 RVTHRES 14 IT 15 17 LGATE GATE 1 RLGATE CIN LDRAIN DPLCAP 10 RSLC1 51 ESLC 50 RDRAIN EVTHRES + 19 8 6 21 16 RLDRAIN DBREAK 11 + 17 EBREAK 18 MWEAK MMED MSTRO LSOURCE 8 RSOURCE RLSOURCE RBREAK 18 RVTEMP 19 VBAT + 7 SOURCE 3 5 DRAIN 2
rev May 2001
RSLC2
5 51 ESG + EVTEMP RGATE + 18 22 9 20 6 8 -
S1B CA
VBAT 22 19 DC 1 ESLC 51 50 VALUE={(V(5,51)/ABS(V(5,51)))*(PWR(V(5,51)/(1e-6*275),5))} .MODEL DBODYMOD D (IS = 3.6e-11 N=1.075 RS = 3.5e-3 TRS1 = 1e-3 TRS2 = 1e-6 XTI=1.0 CJO = 1.45e-9 TT = 8e-11 M = 0.51) .MODEL DBREAKMOD D (RS = 1.7e-1 TRS1 = 1e-3 TRS2 = -8.9e-6) .MODEL DPLCAPMOD D (CJO = 11.5e-10 IS = 1e-30 N = 10 M = 0.46) .MODEL MMEDMOD NMOS (VTO = 1.7 KP = 9 IS=1e-30 N = 10 TOX = 1 L = 1u W = 1u RG = 2.69) .MODEL MSTROMOD NMOS (VTO = 2.1 KP = 100 IS = 1e-30 N= 10 TOX = 1 L = 1u W = 1u) .MODEL MWEAKMOD NMOS (VTO = 1.36 KP = 0.05 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u RG = 26.9 RS = 0.1) .MODEL RBREAKMOD RES (TC1 = 1e-3 TC2 = -7e-7) .MODEL RDRAINMOD RES (TC1 = 1.2e-2 TC2 = 3.0e-5) .MODEL RSLCMOD RES (TC1 = 1e-3 TC2 = 1e-6) .MODEL RSOURCEMOD RES (TC1 = 1e-3 TC2 = 1e-6) .MODEL RVTHRESMOD RES (TC1 = -2.6e-3 TC2 = -7.5e-6) .MODEL RVTEMPMOD RES (TC1 = -1.8e-3 TC2 = 1e-6) .MODEL S1AMOD VSWITCH (RON = 1e-5 .MODEL S1BMOD VSWITCH (RON = 1e-5 .MODEL S2AMOD VSWITCH (RON = 1e-5 .MODEL S2BMOD VSWITCH (RON = 1e-5 .ENDS NOTE: For further discussion of the PSPICE model, consult A New PSPICE Sub-Circuit for the Power MOSFET Featuring Global Temperature Options; IEEE Power Electronics Specialist Conference Records, 1991, written by William J. Hepp and C. Frank Wheatley. ROFF = 0.1 ROFF = 0.1 ROFF = 0.1 ROFF = 0.1 VON = -4.0 VOFF= -0.8) VON = -0.8 VOFF= -4.0) VON = -0.3 VOFF= 0.2) VON = 0.2 VOFF= -0.3)
(c)2003 Fairchild Semiconductor Corporation
+
DBODY
ISL9N306AD3 / ISL9N306AD3ST Rev. B2
ISL9N306AD3 / ISL9N306AD3ST
SABER Electrical Model
REV May 2001 template ISL9N306A n2,n1,n3 electrical n2,n1,n3 { var i iscl dp..model dbodymod = (isl = 3.6e-11, nl=1.075 , rs = 3.5e-3, trs1 = 1e-3, trs2 = 1e-6, xti=1.0, cjo = 1.45e-9, tt = 8e-11, m = 0.51,) dp..model dbreakmod = (rs =0.17, trs1 = 1e-3, trs2 = -8.9e-6) dp..model dplcapmod = (cjo = 11.5e-10, isl=10e-30, nl=10, m=0.46) m..model mmedmod = (type=_n, vto = 1.7, kp=9, is=1e-30, tox=1) m..model mstrongmod = (type=_n, vto = 2.1, kp = 100, is = 1e-30, tox = 1) m..model mweakmod = (type=_n, vto = 1.36, kp = 0.05, is = 1e-30, tox = 1, rs=0.1) sw_vcsp..model s1amod = (ron = 1e-5, roff = 0.1, von = -4.0, voff = -0.8) sw_vcsp..model s1bmod = (ron =1e-5, roff = 0.1, von = -0.8, voff = -4.0) sw_vcsp..model s2amod = (ron = 1e-5, roff = 0.1, von = -0.3, voff = 0.2) LDRAIN sw_vcsp..model s2bmod = (ron = 1e-5, roff = 0.1, von = 0.2, voff = -0.3) DPLCAP 5 DRAIN c.ca n12 n8 = 2.0e-9 c.cb n15 n14 = 2.3e-9 c.cin n6 n8 = 3e-9 dp.dbody n7 n5 = model=dbodymod dp.dbreak n5 n11 = model=dbreakmod dp.dplcap n10 n5 = model=dplcapmod
ESG 10 RSLC1 51 RSLC2 ISCL 6 8 + LGATE GATE 1 RLGATE EVTEMP RGATE + 18 22 9 20 50 RDRAIN EVTHRES 16 21 + 19 8 6 MMED MSTRO CIN 8 RSOURCE RLSOURCE S1A 12 13 8 S1B CA 13 + EGS 6 8 EDS S2A 14 13 S2B CB + 5 8 8 22 RVTHRES 14 IT VBAT + 15 17 RBREAK 18 RVTEMP 19 DBREAK 11 DBODY MWEAK EBREAK + 17 18 LSOURCE 7 SOURCE 3 RLDRAIN 2
i.it n8 n17 = 1 l.ldrain n2 n5 = 1e-9 l.lgate n1 n9 = 4.58e-9 l.lsource n3 n7 = 1.47e-9
m.mmed n16 n6 n8 n8 = model=mmedmod, l=1u, w=1u m.mstrong n16 n6 n8 n8 = model=mstrongmod, l=1u, w=1u m.mweak n16 n21 n8 n8 = model=mweakmod, l=1u, w=1u res.rbreak n17 n18 = 1, tc1 = 1e-3, tc2 = -7e-7 res.rdrain n50 n16 = 1e-3, tc1 = 1.2e-2, tc2 = 3.0e-5 res.rgate n9 n20 = 2.69 res.rldrain n2 n5 = 10 res.rlgate n1 n9 = 45.8 res.rlsource n3 n7 = 14.7 res.rslc1 n5 n51= 1e-6, tc1 = 1e-3, tc2 =1e-6 res.rslc2 n5 n50 = 1e3 res.rsource n8 n7 = 3.5e-3, tc1 = 1e-3, tc2 =1e-6 res.rvtemp n18 n19 = 1, tc1 = -1.8e-3, tc2 = 1e-6 res.rvthres n22 n8 = 1, tc1 = -2.6e-3, tc2 = -7.5e-6 spe.ebreak n11 n7 n17 n18 = 35.8 spe.eds n14 n8 n5 n8 = 1 spe.egs n13 n8 n6 n8 = 1 spe.esg n6 n10 n6 n8 = 1 spe.evtemp n20 n6 n18 n22 = 1 spe.evthres n6 n21 n19 n8 = 1 sw_vcsp.s1a n6 n12 n13 n8 = model=s1amod sw_vcsp.s1b n13 n12 n13 n8 = model=s1bmod sw_vcsp.s2a n6 n15 n14 n13 = model=s2amod sw_vcsp.s2b n13 n15 n14 n13 = model=s2bmod v.vbat n22 n19 = dc=1
equations { i (n51->n50) +=iscl iscl: v(n51,n50) = ((v(n5,n51)/(1e-9+abs(v(n5,n51))))*((abs(v(n5,n51)*1e-6/275))** 5)) } }
(c)2003 Fairchild Semiconductor Corporation
ISL9N306AD3 / ISL9N306AD3ST Rev. B2
ISL9N306AD3 / ISL9N306AD3ST
SPICE Thermal Model
REV May 2001 ISL9N306AT CTHERM1 th 6 2.7e-4 CTHERM2 6 5 3.9e-3 CTHERM3 5 4 4.2e-3 CTHERM4 4 3 4.8e-3 CTHERM5 3 2 1.9e-2 CTHERM6 2 tl 5.9e-2 RTHERM1 th 6 1.0e-3 RTHERM2 6 5 4.8e-3 RTHERM3 5 4 4.5e-2 RTHERM4 4 3 2.6e-1 RTHERM5 3 2 3.1e-1 RTHERM6 2 tl 3.4e-1
th
JUNCTION
RTHERM1
CTHERM1
6
RTHERM2
CTHERM2
5
SABER Thermal Model
SABER thermal model ISL9N306AT template thermal_model th tl thermal_c th, tl { ctherm.ctherm1 th 6 = 2.7e-4 ctherm.ctherm2 6 5 = 3.9e-3 ctherm.ctherm3 5 4 = 4.2e-3 ctherm.ctherm4 4 3 = 4.8e-3 ctherm.ctherm5 3 2 = 1.9e-2 ctherm.ctherm6 2 tl = 5.9e-2 rtherm.rtherm1 th 6 = 1.0e-3 rtherm.rtherm2 6 5 = 4.8e-3 rtherm.rtherm3 5 4 = 4.5e-2 rtherm.rtherm4 4 3 = 2.6e-1 rtherm.rtherm5 3 2 = 3.1e-1 rtherm.rtherm6 2 tl = 3.4e-1 }
RTHERM3
CTHERM3
4
RTHERM4
CTHERM4
3
RTHERM5
CTHERM5
2
RTHERM6
CTHERM6
tl
CASE
(c)2003 Fairchild Semiconductor Corporation
ISL9N306AD3 / ISL9N306AD3ST Rev. B2
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FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, or (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in significant injury to the user.
2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness.
PRODUCT STATUS DEFINITIONS Definition of Terms
Datasheet Identification Advance Information Product Status Formative or In Design First Production Definition This datasheet contains the design specifications for product development. Specifications may change in any manner without notice. This datasheet contains preliminary data, and supplementary data will be published at a later date. Fairchild Semiconductor reserves the right to make changes at any time without notice in order to improve design. This datasheet contains final specifications. Fairchild Semiconductor reserves the right to make changes at any time without notice in order to improve design. This datasheet contains specifications on a product that has been discontinued by Fairchild semiconductor. The datasheet is printed for reference information only.
Preliminary
No Identification Needed
Full Production
Obsolete
Not In Production
Rev. I2

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